`timescale 1ns / 100ps
module par_ser_tb();

reg        sh_clk_tb;
reg        rst_tb;
reg        load_tb;
reg  [7:0] par_in_tb;
wire       ser_out_tb;

// clock signal generation (period = 20)
initial
begin
    sh_clk_tb <= 1'b0;
    forever #10 sh_clk_tb <= ~sh_clk_tb;
end

// reset signal generation
initial
begin
    rst_tb <= 1'b0;
    #5 rst_tb <= 1'b1;
    #5 rst_tb <= 1'b0;
end

// load signal generation
initial
begin
    load_tb <= 1'b0;
    #40  load_tb <= 1'b1;
    #160 load_tb <= 1'b0;
    #20  load_tb <= 1'b1;
    #20  load_tb <= 1'b0;
    #20  load_tb <= 1'b1;
end    

// parallel input generation
initial
begin
    par_in_tb <= 8'h00;
    #20  par_in_tb <= 8'h12;
    #40  par_in_tb <= 8'h34;
    #120  par_in_tb <= 8'h86;
    #60  par_in_tb <= 8'h78;
end    

// DUT instance
par_ser_beh1 par_ser_inst(
.sh_clk(sh_clk_tb),    // shift clock
.rst(rst_tb),          // reset
.load(load_tb),        // load enable
.par_in(par_in_tb),    // parallel input
.ser_out(ser_out_tb)); // serial output

endmodule